The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption algorithm, including a generalized Arnold map for the permutation. The encryption scheme demonstrated its efficiency through statistical tests, key sensitivity analysis and resistance to brute force and differential attacks. The fractional-order memristive system includes a reconfigurable coordinate rotation digital computer (CORDIC) and Grünwald–Letnikov (GL) architectures, which are essential for trigonometric and hyperbolic functions and fractional-order operator implementations, respectively. The proposed system was implemented on the Artix-7 FPGA board, achieving a throughput of 0.396 Gbit/s. © 2023 by the authors.
FPGA REALIZATION OF COMPLEX LOGISTIC MAP FRACTAL BEHAVIOR
This paper studies the capability of digital architecture to mimic fractal behavior. As chaotic attractors realized digitally had opened many tracks, digital designs mimicking fractals may ultimately achieve the same. This study is based on a complex single-dimensional discrete chaotic system known as the generalized positive logistic map. The fractals realized from this system are linked to the results of the mathematical analysis to understand the fractal behavior with different variations. A digital hardware architecture manifesting the fractal behavior is achieved on FPGA, showing a fractal entity experimentally. With this digital realization, it is hoped that fractals can follow the example of chaotic attractors digital applications. © 2022 World Scientific Publishing Company.
Numerical Sensitivity Analysis and Hardware Verification of a Transiently-Chaotic Attractor
We introduce a new chaotic system with nonhyperbolic equilibrium and study its sensitivity to different numerical integration techniques prior to implementing it on an FPGA. We show that the discretization method used in numerically integrating the set of differential equations in MATLAB and Mathematica does not yield chaotic behavior except when a low accuracy Euler method is used. More accurate higher-order numerical algorithms (such as midpoint and fourth-order Runge-Kutta) result in divergence in both MATLAB and Mathematica (but not Python), which agrees with the divergence observed in an analog circuit implementation of the system. However, a fixed-point digital FPGA implementation confirms the chaotic behavior of the system using Euler and fourth-order Runge-Kutta realizations. Therefore, the increased sensitivity of chaotic systems with nonhyperbolic equilibrium should be carefully considered for reproducibility. © 2022 World Scientific Publishing Company.
Generalized synchronization of different dimensional integer-order and fractional order chaotic systems
In this work different control schemes are proposed to study the problem of generalized synchronization (GS) between integer-order and fractional order chaotic systems with different dimensions. Based on Lyapunov stability theory of integer-order differential systems, fractional Lyapunov-based approach and nonlinear controllers, different criterions are derived to achieve generalized synchronization. The effectiveness of the proposed control schemes are verified by numerical examples and computer simulations. © Springer International Publishing AG 2017.
A study of the nonlinear dynamics of human behavior and its digital hardware implementation
This paper introduces an intensive discussion for the dynamical model of the love triangle in both integer and fractional-order domains. Three different types of nonlinearities soft, hard, and mixed between soft and hard, are used in this study. MATLAB numerical simulations for the different three categories are presented. Also, a discussion for how the kind of personalities affects the behavior of chaotic attractors is introduced. This paper suggests some explanations for the complex love relationships depending on the impact of memory (IoM) principle. Lyapunov exponents, Kaplan-Yorke dimension, and bifurcation diagrams for three different integer-order cases show a significant dependency on system parameters. Hardware digital realization of the system is done using the Xilinx Artix-7 XC7A100T FPGA kit. Version 14.7 from the Xilinx ISE platform is used in both Verilog simulation and hardware implementation stages. The digital approach of such a system opens the door to predict the love relation after sensing the human personality. Also, this study will help in justifying more human emotions like happiness, panic, and fear accurately. Perhaps shortly, this study may combine with artificial intelligence to demonstrate Human-Computer interaction products. © 2020
A novel image encryption system merging fractional-order edge detection and generalized chaotic maps
This paper presents a novel lossless image encryption algorithm based on edge detection and generalized chaotic maps for key generation. Generalized chaotic maps, including the fractional-order, the delayed, and the Double-Humped logistic maps, are used to design the pseudo-random number key generator. The generalization parameters add extra degrees of freedom to the system and increase the keyspace achieving more secure keys. Fractional order edge detection filters exhibited better noise robustness than the conventional integer-order ones, rendering the system to be suitable for medical imaging security. The proposed system flexibly integrate different edge detectors, as well as various logistic maps for key generation. The sensitivity of the chaotic maps to all parameters guarantees the encryption system key sensitivity. Security analyses aspects assure the efficiency of the proposed algorithm performance, having high pixel correlation coefficients and flat histograms of cipher images reported. A comparison between the proposed scheme with existing cryptosystems is also presented, regarding histogram uniformity, contrast analysis, Shannon entropy measurements. Compared to the state of the art algorithms, the proposed algorithm has higher statistical and cryptanalytic properties. © 2019
FPGA realization of fractals based on a new generalized complex logistic map
This paper introduces a new generalized complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the stability conditions, bifurcation behavior and maximum Lyapunov exponent (MLE). A relation between the mathematical analysis and fractal behavior is demonstrated, which enables formulating the fractal limits. A compact fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior is validated experimentally on Artix-7 FPGA board. Two examples of fractal implementation are verified, yielding frequencies of 34.593 MHz and 31.979 MHz and throughputs of 0.415 Gbit/s, 0.384 Gbit/s. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications. © 2021 Elsevier Ltd
DISH: Digital image steganography using stochastic-computing with high-capacity
Stochastic computing is a relatively new approach to computing that has gained interest in recent years due to its potential for low-power and high-noise environments. It is a method of computing that uses probability to represent and manipulate data, therefore it has applications in areas such as signal processing, machine learning, and cryptography. Stochastic steganography involves hiding a message within a cover image using a statistical model. Unlike traditional steganography techniques that use deterministic algorithms to embed the message, stochastic steganography uses a probabilistic approach to hide the message in a way that makes it difficult for an adversary to detect. Due to this error robustness and large bit streams stochastic computing, they are well suited for high capacity and secure image steganography. In this paper, as per the authors’ best knowledge, image steganography using stochastic computing based on linear feedback shift register (LFSR) is proposed for the first time. In the proposed technique, the cover image is converted to stochastic representation instead of the binary one, and then a secret image is embedded in it. The resulting stego image has a high PSNR value transmitted with no visual trace of the hidden image. The final results are stego image with PSNR starting from 30 dB and a maximum payload up to 40 bits per pixel (bpp) with an effective payload up to 28 bpp. The proposed method achieves high security and high capability of the number of stored bits in each pixel. Thus, the proposed method can prove a vital solution for high capacity and secure image steganography, which can then be extended to other types of steganography. © 2024, The Author(s).
Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA
Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts © 2023 Elsevier GmbH
Software and hardware realizations for different designs of chaos-based secret image sharing systems
Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis. © The Author(s) 2024.