In this paper, a general analysis of the fractional order operational transresistance amplifiers (OTRA) based oscillator is presented and validated through eight different circuits which represent two classifications according to the number of OTRAs. The general analytical formulas of the oscillation frequency, condition as well as the phase difference are illustrated for each case and summarized in tables. One of the advantages of the fractional-order circuit is the extra degrees of freedom added from the fractional-order parameters. Moreover different special cases {? = ? ? 1, ? ? ? = 1, ? ? ? = 1} are investigated where the conventional case ? = ? = 1 is included in all of them. Also, the effect of the fractional order parameter on the phase difference between the two oscillator outputs is presented which increases the design flexibility and controllability. The effect of the non-ideal characteristics associated with OTRA on the presented oscillator is also studied. A comparison between the fractional order oscillators with their integer order counterpart is also presented to verify the advantages of the added fractional order parameters. Numerical and spice simulations are given to validate the presented analysis. © 2015 Elsevier GmbH.
Fractional Order Sallen–Key and KHN Filters: Stability and Poles Allocation
This paper presents the analysis for allocating the system poles and hence controlling the system stability for KHN and Sallen–Key fractional order filters. The stability analysis and stability contours for two different fractional order transfer functions with two different fractional order elements are presented. The effect of the transfer function parameters on the singularities of the system is demonstrated where the number of poles becomes dependent on the transfer function parameters as well as the fractional orders. Numerical, circuit simulation, and experimental work are used in the design to test the proposed stability contours. © 2014, Springer Science+Business Media New York.
On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA
This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.
An inductorless CMOS realization of Chua’s circuit
In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst. – I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New Gm-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 ?m Mietec process are presented. © 2003 Published by Elsevier Science Ltd.
MOS realization of the conjectured simplest chaotic equation
This paper presents a general block diagram of a third-order linear differential equation using current mode techniques. The realization of the conjectured simplest chaotic equation of Elwakil and Kennedy based on G m – C technology is given. The metal oxide semiconductor circuit is composed of 20 transistors and three grounded capacitors, can operate from a supply voltage as low as ± 1.5 V, and covers a very wide range of frequencies. PSpice simulation results using 0.5 ?m Mietec technology are given. A numerical solution is also included to verify the circuit operation.
MOS realization of the double-scroll-like chaotic equation
This brief presents a new chaotic circuit based on Gm-C integrators. The circuit realizes the double-scroll-like chaotic equation presented in [1], [2]. The mentioned equation describes double-scroll dynamics with a simple mathematical model. The proposed circuit uses a current-mode technique that is suitable for integrated circuit implementation and high-frequency operation using low supply voltage. A general block diagram is presented based on Gm-C integrators. Its realization using MOS transistors and three grounded capacitors is also given. Simulation results to demonstrate the practicality of the circuit are included.
Reconfigurable chaotic pseudo random number generator based on FPGA
This paper presents an FPGA Pseudo Random Number Generator (PRNG) that is based on the Lorenz and Lü chaotic systems. These two systems are used to generate four different 3D chaotic attractors. One attractor is generated from Lorenz while the other three attractors are generated from Lü. The output attractor of the proposed PRNG can be reconfigured during real time operation using an efficient hardwired shifting and multiplexing scheme. Furthermore, in order to exploit the proposed reconfiguration feature, the proposed PRNG has been embedded in an FPGA cascaded encryption processor that ciphers the input data from one up to four times successively. In each ciphering operation the PRNG is set to a new configuration and is initialized according to a part of the encryption key. The size of the encryption key can be varied according to the number of required ciphering operations. The proposed PRNG has been realized using VHDL, synthesized on Xilinx using the FPGA device XC5VLX50T, and analyzed using MATLAB and the NIST statistical suite. The proposed PRNG has utilized only 1.4% from the FPGA’s slices, achieved an operating frequency up to 78 MHz, and successfully passed all the NIST statistical tests. © 2018 Elsevier GmbH
A switched chaotic encryption scheme using multi-mode generalized modified transition map
This paper presents a multi-mode generalized modified transition chaotic map and a switched chaotic encryption scheme based on it
MOS realization of the modified Lorenz chaotic system
A new chaotic oscillator circuit that realizes three attractors, the modified Lorenz system, Lorenz attractor “Butterfly attractor” and unsymmetrical modified Lorenz system [IEEE Trans
On The Optimization of Fractional Order Low-Pass Filters
This paper presents three different optimization cases for normalized fractional order low-pass filters (LPFs) with numerical, circuit and experimental results