Recently, the mem-elements-based circuits have been addressed frequently in the nonlinear circuit theory due to their unique behavior. Thus, the modeling and characterizing of the mem-elements has become essential, especially studying their response under any excitation signal. This paper investigates the response of the meminductor under DC, sinusoidal, and periodic current signals for the first time. Furthermore, a meminductor emulator is developed to fit the obtained formulas which are built using commercial off the shelf components. The proposed analysis offers closed form expressions for the meminductance for each case. Moreover, many fundamentals and properties are derived to understand the responses such as the maximum saturation time in case of the DC response. A general closed form expression for the meminductance is derived under any periodic waveform, and this formula has been validated by applying a square wave as an example. © 2013 Springer Science+Business Media New York.
Enhanced removal of crystal violet using rawfava bean peels, its chemically activated carbon compared with commercial activated carbon
Crystal violet is a basic dye that is widely used by various industries, such as textiles and paints. These industries discharge their effluents, contaminated with crystal violet, into water streams, and these effluents have an adverse effect on aquatic organisms, the environment, and human health. Crystal violet is a basic dye that is widely used by various industries, such as textiles and paints. These industries discharge their effluents, contaminated with crystal violet, into water streams, and these effluents have an adverse effect on aquatic organisms, the environment, and human health. Hence, this paper is directed at studying the removal of crystal violet using environmentally friendly, cost-effective adsorbent materials such as raw fava bean (RFP-H3F), and chemically activated carbon (H3F) in comparison to commercial activated carbon (CAC).Various characterization techniques are applied, such as XRD, FT-IR,and SEM analyses. Then, the process of optimizing is shown through some preliminary experiments and a Response Surface Methodology (RSM) experiment to find the best conditions for removing crystal violet efficiently. Results revealed that the raw fava bean peels and the commercial activated carbon have the maximum removal efficiency of 95 %, and 83 % respectively, after 180 min of contact time. It is hypothesized that raw fava bean peels (RFP) and chemically activated carbon using phosphoric acid RFP-H3F will exhibit comparable efficiency in removing crystal violet when compared to commercial activated carbon (CAC). Various characterization techniques, including X-ray diffraction (XRD), Fourier-transform infrared spectroscopy (FT-IR),and scanning electron microscopy (SEM), are applied to analyze the properties of the adsorbent materials. Afterwards, the optimization process is displayed through some preliminary experiments followed by a Response Surface Methodology (RSM) experiment to obtain the optimum conditions, which achieve high crystal violet removal efficiency. The results demonstrate that both raw fava bean peels and commercial activated carbon exhibit significant removal efficiencies, with raw fava bean peels achieving a maximum removal efficiency of 95 % and commercial activated carbon achieving 83 %. © 2023 The Authors
Memristor-based voltage-controlled relaxation oscillators
This paper introduces two voltage-controlled memristor-based reactance-less oscillators with analytical and circuit simulations. Two different topologies which are R-M and M-R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor-based voltage-controlled oscillator (VCO) is introduced as an application for the proposed circuits which is nano-size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.
Reconfigurable hardware implementation of K-nearest neighbor algorithm on FPGA
Nowadays, Machine Learning is commonly integrated into most daily life applications in various fields. The K Nearest Neighbor (KNN), which is a robust Machine Learning algorithm, is traditionally used in classification tasks for its simplicity and training-less nature. Hardware accelerators such as FPGAs and ASICs are greatly needed to meet the increased requirements of performance for these applications. It is well known that ASICs are non-programmable and only fabricated once with high expenses, this makes the fabrication of a complete chip for a specific classification problem inefficient. As a better alternative to this challenge, in this work, a reconfigurable hardware architecture of the KNN algorithm is proposed where the employed dataset, the algorithm parameters, and the distance metric used to evaluate the nearest neighbors are all updatable after fabrication, in the ASIC case, or after programming, in the FPGA case. The architecture is also made flexible to accommodate different memory requirements and allow variable arithmetic type and precision selection. Both parameters can be adjusted before fabrication to account only for the expected memory requirement and the fixed point precision required or floating point arithmetic if needed. The proposed architecture is realized on the Genesys 2 board based on Xilinx’s Kintex-7 FPGA. The results obtained from the experiment are consistent with those obtained from the simulation and software analysis. The proposed realization reaches a frequency of up to around 110 MHz and a power consumption of less than 0.4 watts © 2023 Elsevier GmbH
Software and hardware realizations for different designs of chaos-based secret image sharing systems
Secret image sharing (SIS) conveys a secret image to mutually suspicious receivers by sending meaningless shares to the participants, and all shares must be present to recover the secret. This paper proposes and compares three systems for secret sharing, where a visual cryptography system is designed with a fast recovery scheme as the backbone for all systems. Then, an SIS system is introduced for sharing any type of image, where it improves security using the Lorenz chaotic system as the source of randomness and the generalized Arnold transform as a permutation module. The second SIS system further enhances security and robustness by utilizing SHA-256 and RSA cryptosystem. The presented architectures are implemented on a field programmable gate array (FPGA) to enhance computational efficiency and facilitate real-time processing. Detailed experimental results and comparisons between the software and hardware realizations are presented. Security analysis and comparisons with related literature are also introduced with good results, including statistical tests, differential attack measures, robustness tests against noise and crop attacks, key sensitivity tests, and performance analysis. © The Author(s) 2024.
On-the-Fly Parallel Processing IP-Core for Image Blur Detection, Compression, and Chaotic Encryption Based on FPGA
This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard 256times 256 images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out. © 2013 IEEE.
An inductorless CMOS realization of Chua’s circuit
In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst. – I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New Gm-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 ?m Mietec process are presented. © 2003 Published by Elsevier Science Ltd.
MOS realization of the conjectured simplest chaotic equation
This paper presents a general block diagram of a third-order linear differential equation using current mode techniques. The realization of the conjectured simplest chaotic equation of Elwakil and Kennedy based on G m – C technology is given. The metal oxide semiconductor circuit is composed of 20 transistors and three grounded capacitors, can operate from a supply voltage as low as ± 1.5 V, and covers a very wide range of frequencies. PSpice simulation results using 0.5 ?m Mietec technology are given. A numerical solution is also included to verify the circuit operation.
Secure blind watermarking using Fractional-Order Lorenz system in the frequency domain
This paper investigates two different blind watermarking systems in the frequency domain with the development of a Pseudo Random Number Generator (PRNG), based on a fractional-order chaotic system, for watermark encryption. The methodology is based on converting the cover image to the YCbCr color domain and applying two different techniques of frequency transforms, Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT), to the Y channel. Then, the encrypted watermark is embedded in the middle-frequency band and HH band coefficients for the DCT and DWT, respectively. For more security and long encryption key size, the fractional-order Lorenz system is used to double the encryption key size and make it secure against brute-force attacks. The proposed algorithms successfully detect the hidden watermark by using the statistical properties of the embedding media, where the PRNG is examined using statistical tests and the watermarking systems are evaluated using standard imperceptibility and robustness measures. Common attacks such as noise-adding attacks, image enhancement attacks and geometric transformation attacks are discussed. Results of the PRNG demonstrate sensitivity to the system parameters, and results of the watermarking systems show good imperceptibility while keeping the robustness measures in a good range. © 2023 Elsevier GmbH
Analysis and Guidelines for Different Designs of Pseudo Random Number Generators
The design of an efficient Pseudo Random Number Generator (PRNG) with good randomness properties is an important research topic because it is a core component in many applications. Based on an extensive study of most PRNGs in the past few decades, this paper categorizes six distinct design scenarios under two primary groups: non-chaotic and chaotic generators. The non-chaotic group comprises Linear Feedback Shift Registers (LFSR) with S-Boxes, primitive roots, and elliptic curves, whereas the chaotic group encompasses discrete, continuous, and fractional-order chaotic generators. This paper delves into the related scientific summaries, equations, flowcharts, and designs with necessary recommendations for each PRNG scenario. Even though the focus is on the basic design characteristics that provide simple, functional and secure PRNGs, it is possible to enhance those designs for additional features and improved efficiency. Simulation outcomes and system key configurations, which produce long random sequences, are also presented and evaluated using leading criteria. The evaluation criteria include the National Institute of Standards and Technology (NIST) SP-800-22 test suite, TestU01 randomness tests, histogram, entropy, autocorrelation, and cross-correlation. Furthermore, key space, key sensitivity, and bit rate indicate that all designed examples meet international standards with high quality. The presented PRNGs are compared and integrated into an image encryption system. Although each PRNG design scenario can have a different key space, simple designs with fixed-length system keys are chosen for the sake of proper comparisons. Statistical and security assessments of the encryption system demonstrate that the PRNGs are cryptographically secure. © 2013 IEEE.