This paper summarizes the symmetric image encryption results of 27 different algorithms, which include substitution-only, permutation-only or both phases
Memristor FPGA IP core implementation for analog and digital applications
Exploring the nonlinear dynamics of the memristors is essential to be adequately used in the applications
Digital Emulation of a Versatile Memristor with Speech Encryption Application
Memristor characteristics such as nonlinear dynamics, state retention and accumulation are useful for many applications
Generalized hardware post-processing technique for chaos-based pseudorandom number generators
This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback
Multiplierless chaotic Pseudo random number generators
This paper presents a multiplierless based FPGA implementation for six different chaotic Pseudo Random Number Generators (PRNGs) that are based on: Chua, modified Lorenz, modified Rössler, Frequency Dependent Negative Resistor (FDNR) oscillator, and other two systems that are modelled using the simple jerk equation
Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77 Gbits/s
This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation
High-Frequency Capacitorless Fractional-Order CPE and FI Emulator
A fractional-order capacitor and inductor emulator, implemented using MOS transistors, instead of passive capacitors, is introduced in this paper
On the stability of linear systems with fractional-order elements
Linear integer-order circuits are a narrow subset of rational-order circuits which are in turn a subset of fractional-order
Stability analysis of fractional-order Colpitts oscillators
The mathematical formulae of six topologies of fractional-order Colpitts oscillator are introduced in this paper
Realization of fractional-order capacitor based on passive symmetric network
In this paper, a new realization of the fractional capacitor (FC) using passive symmetric networks is proposed