In this work, we recall the generalized exponential function in the fractional-order domain which enables defining generalized cosine and sine functions. We then re-visit some important trigonometric identities and generalize them from the narrow integer-order subset to the more general fractional-order domain. Generalized hyperbolic function relations are also given. © 2011 IEEE.
Mathematical analysis of gene regulation activator model
This paper presents a complete analysis of the mathematical model of the gene regulation process. The model describes the induced gene expression under the effect of activators. The model differential equations are solved analytically, and the exact solution of the gene model is introduced. Moreover, a study of the model dynamics, including the fixed points and stability conditions are presented. The parameters effects on the phase plane portraits and the transient responses of the mRNA as well as the protein concentrations are intensively detailed. This work serves as a brick stone towards a complete model for a complete gene regulation biological process for future prediction and control of diseases at the genetic level. © 2018 IEEE.
Image encryption based on double-humped and delayed logistic maps for biomedical applications
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the one dimensional double humped logistic map as well as the two-dimensional delayed logistic map. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE, NPCR as well as UACI measurements. The encryption system is proven to be highly sensitive to ±0.001% perturbation of the logistic maps parameters. The system is tested on medical images of palm print as well as Parkinson disease MRI images. © 2017 IEEE.
Reconstruction of target properties for different distributions using transient adjoint technique
This paper discusses the sensitivity analysis and the inverse problem solution using the Adjoint Variable Method (AVM) integrated with Transmission Line Modeling (TLM) for many examples having different distributions. The sensitivity analyses of the Gaussian function relative to its parameters is introduced where, great discrimination is observed of the sensitivity magnitude which reflects on the electromagnetic sensitivity and the solution of the inverse problem. Different obstacles with properties (? r, ?) having Gaussian, Poisson and exponential distributions are investigated.
Analog fault diagnosis by inverse problem technique
A novel algorithm for detecting soft faults in linear analog circuits based on the inverse problem concept is proposed. The proposed approach utilizes optimization techniques with the aid of sensitivity analysis. The main contribution of this work is to apply the inverse problem technique to estimate the actual parameter values of the tested circuit and so, to detect and diagnose single fault in analog circuits. The validation of the algorithm is illustrated through applying it to Sallen-Key second order band pass filter and the results show that the detecting percentage efficiency was 100% and also, the maximum error percentage of estimating the parameter values is 0.7%. This technique can be applied to any other linear circuit and it also can be extended to be applied to non-linear circuits. © 2011 IEEE.
Built-in-current-sensor for testing short and open faults in CMOS digital circuits
In this paper, a novel built-in sensor (BIS) for digital CMOS circuit testing has been proposed. The proposed BIS has no voltage degradation and it is able to detect, identify and localize both open and short circuit faults. Moreover, it has a simple realization with very small area and detection time. A 4×4 multiplier cell is tested by the proposed BIS and all injected faults are detected. © 2009 IEEE.
A Simple BJT Inverse Memristor Emulator and Its Application in Chaotic Oscillators
A generalized inverse memristor emulator is proposed based on two BJT transistors as a diode connected with a first order parallel RC filter. The mathematical model of the circuit is presented where the pinched hysteresis loops (PHLs) with different periodic stimuli are analyzed. The numerical, P-Spice simulations and experimental results are presented indicating that the introduced emulator is a simple voltage-controlled generalized inverse memristor. The results show that the PHLs area is increased with increasing the applied frequency. In addition, the proposed emulator is employed in a simple chaotic circuit. The effect of the inductor’s values on the chaotic system is investigated and the P-Spice simulations are performed to approve the numerical results. © 2019 IEEE.
FPGA Speech Encryption Realization Based on Variable S-Box and Memristor Chaotic Circuit
This paper introduces a new encryption/decryption scheme based on a dynamic substitution box concept. Values of the proposed S-Box are different for each sample depending on the behavior of a memristor-based chaotic system. MATLAB simulations and FPGA implementation for the circuit are presented with throughput 4.266 Gbit/s. Also, FPGA realization for encryption/decryption scheme is proposed. Entropy, MSE, correlation coefficient tests are applied on two different input files to examine the efficiency of this cryptosystem. © 2018 IEEE.
Memristor-CNTFET based Ternary Comparator unit
This paper proposes a new design for ternary logic comparator unit based on memristive threshold logic concept. To provide high-performance design, integrating memristor and Carbon Nano-Tube Field-Effect Transistor, CNTFET, is used. A comparison with other related work is presented to discuss performance aspects. It shows that performance has been improved by 75% compared with the other related work. Therefore, the proposed design is very promising to build high-performance full ternary ALU memristor-based unit. © 2018 IEEE.
Memristor-based balanced ternary adder
This paper introduces a memristor based ternary adder, which is an essential building block for any arithmetic ternary operations. The proposed ternary adder circuit tries to achieve the theoretical advantages of the ternary system, increase the density and decrease the processing time by using the memristor properties such as its hysteresis and nanotechnology. The general block diagram of the proposed circuit is illustrated based on memristors and its operation has been validated via different examples using PSPICE where simulation results show a great match. © 2013 IEEE.