A novel topology for simultaneous emulation of fractional-order capacitors and inductors is presented in this paper. In particular, only one control terminal is used in order to select the type of the element as well as its fractional order. This is achieved through an appropriate fitting of the expressions of the intermediate bias currents, in such a way that, eventually, only the adjustment of one main bias current is required. The performance of the proposed topology is evaluated through post-layout simulations using Cadence and Austria Mikro Systeme (AMS) 0.35?m CMOS process. © 2019 Elsevier GmbH
Kapoulea S., Psychalinos C., Elwakil A.S., Radwan A.G.
Fractional-order capacitors; Fractional-order circuits; Fractional-order impedance; Fractional-order inductors
AEU – International Journal of Electronics and Communications, Vol. 103, PP. 32 to 45, Doi: 10.1016/j.aeue.2019.03.002