We propose a mathematical system capable of exhibiting chaos with a chaotic attractor which is odd symmetrical in the x ? y phase plane but even symmetrical in the x ? z and y ? z phase planes respectively. A hardware implementation of the system is done on a digital FPGA platform for verification. The system is also attractive in the sense that (i) its dynamics are single-parameter controlled and (ii) it inherently generates two chaotic clock signals. As an application, an FPGA design methodology using this oscillator for speech encryption is demonstrated. The security of the proposed encryption scheme is evaluated and results confirm its robustness. Due to the efficient hardware resource utilization, the encrypted system delivers a throughput of 1.3Gbit/sec using a Xilinx Kintex 7. © 2020 Elsevier B.V.
Tolba M.F., Elwakil A.S., Orabi H., Elnawawy M., Aloul F., Sagahyroon A., Radwan A.G.
Circuit oscillations; Field programmable gate arrays (FPGA); Chaotic attractors; Chaotic oscillators; Encryption schemes; FPGA implementations; Hardware implementations; Hardware resource utilization; Single parameter; Speech encryption; Cryptography
Integration, Vol. 72, PP. 163 to 170, Doi: 10.1016/j.vlsi.2020.02.003